The present invention relates to a delay calculation method and to a layout optimization method for high-accuracy delay time calculation of cells and wires in timing verification during the design of a semiconductor integrated circuit. Today, because of advances in semiconductor process technology, the size of transistors have been miniaturized and reduced down to less than 0.5 xcexcm (submicron size). Also with respect to rooting of wires, both the wire pitch and the wire width tend toward being shrunk. Therefore, when calculating a length of time taken for a signal to propagate in a large-scale integrated circuit (hereinafter called the xe2x80x9cdelay timexe2x80x9d), it now becomes necessary to pay attention to the influence of the resistance of a wire and the influence of an adjacent wire. These influences have not been taken into much consideration so far.
For the development of high-integration, high-function, high-performance semiconductor LSI circuits, several techniques have been proposed or already put into practice for high-accuracy calculation of the delay time of a wire between cells forming the aforesaid delay time and the delay time of the cells.
Hereinafter, a conventional, post-layout design flow and a cell delay time/wire delay time calculation process procedure will be explained by making reference to FIG. 13. Note that throughut the specification the term xe2x80x9ccellxe2x80x9d is so defined as to include not only a logical unit such as an inverter and a buffer but also a functional macroblock. Further, the term xe2x80x9cinstancexe2x80x9d is the name for the purpose of identifying cells as different cells even when they have the same logic. This will be explainedtusing a concrete example (FIG. 14). Both an instance 1400 and an instance 1401 are buffer cells. However, in order to deal with these instances as different components, they are named the instance 1400 and the instance 1401.
A conventional design flow and its associated delay calculation method will be described (FIG. 13).
In the layout step S1300 of the design flow (FIG. 13), a delay library 1300 is used to generate a layout 1301 corresponding to a net list 1101. In the layout step S1300, a delay calculation tool mounted in the layout tool is used for timing driven layout in which placement/wire routing is carried out while performing instance and wire delay time. calculations. In the timing driven layout, a layout step is carriel out according to the timing calculated by the delay calculation tool, which is a possible reason for reduction in returning back to a particular design step due to timing errors of a subsequent design flow. However, when performing a timing driven layout in the layout step S1300, if a delay calculation algorithm different from one used in the delay calculation step S1302 is employed, this causes these two steps to produce different delay calculation results. For this reason, the problem with a layout by the timing driven layout is that the design flow is returned back to a particular design step due to the fact that different delay calculation algorithms produce different delay calculation results.
However, even when both the delay calculation tool and the layout tool employ the same delay calculation algorithm, if the layout step S1300 generates a layout shape that does not allow the delay calculation algorithm to perform delay calculations at high accuracy, this results in poor delay calculation accuracy.
Here, by xe2x80x9cthe layout shapexe2x80x9d is meant the shape of a cell, the drive power of a cell, or the like in a layout. In the timing driven layout, a layout step is carried out while the cell delay time, input slew rate, load capacitance, and wire delay time are calculated from the shape.
Therefore, the layout step S1300 is required to generate a layout having such a layout shape capable of allowing high-accuracy delay calculations in the delay calculation step S1302 for timing error reduction and reduction in returning back to a particular design step due to poor delay calculation accuracy. However, such a measure has not yet been taken so far.
Next, in the RC extraction step S1301, the layout 1301 is input and wire parasitic resistance and capacitance are extracted to generate RC information 1102. This RC information 1102 can be expressed in various formats such as DSPF (Standard Parasitic Format: Cadence Design Systems, xe2x80x9cCadence Standard Parasitic Formatxe2x80x9d, August 1993).
This is followed by the delay calculation step S1302 in which the RC information 1102 and the delay library 1300 are input and the delay times of an instance and a wire in the layout 1301 are calculated and delay information 1302 is output.
Further, in the timing simulation step S1303, while the net list 1101 is collated with the delay information 1302, a timing simulation is carried out to provide a simulation result 1303. The LSI designer looks at the simulation result 1303 and if an timing error is output, then the LSI designer returns back to a necessary design step to redo the design.
As the delay calculation method available in the delay calculation step S1302, there are several types of delay time calculation methods. These delay calculation methods will be explained below.
Whereas one of the delay calculation methods (FIG. 14) does not closely deal with the propagation of a signal waveform, the other delay calculation method (FIG. 16) closely deals with the propagation of a signal waveform.
Each of these delay calculation methods will be described. FIG. 14(a) is a conceptual diagram showing a concept relating to the propagation of a waveform for the first delay calculation method. FIG. 14(b) is a diagram showing a procedure of the first delay calculation method. FIG. 14(c) is a diagram showing the division of the first delay calculation method.
The first delay calculation method of FIG. 14(a) is characterized in that the signal waveform propagation between an input and output of a wire 1402 driven by the instance 1400 is calculated and the signal waveform propagation between the input and output terminals of each instance 1400 and 1401 is not taken into consideration.
As more concretely shown in FIG. 14(b), in the instance output signal waveform calculation step, giving attention to the fact that the instance 1400 drives the wire 1402 and the instance 1401, a circuit equation at the output terminal of the instance 1400 is set up. Then, the circuit equation is solved thereby to calculate a signal waveform (or an input signal waveform of the wire 1402) 1404 at the output terminal of the instance 1400.
Next, in the wire output signal waveform calculation step, if the signal waveform 1404 is fed to the wire 1402, then a circuit equation at the output of the wire 1402 is set up. Then, the circuit equation is solved thereby to calculate a signal waveform 1405 at the output of the wire 1402, i.e., an input signal waveform of the instance 1401.
These two steps described above are repeatedly performed on every instance and wire thereby to calculate signal waveforms at the input and output terminals of all the instances for instance delay time calculation and wire delay time calculation.
The algorithm of the first delay calculation method is characterized in that a wire and an instance that is connected to the wire are single split units 1407 and 1408 (see FIG. 14(c)). These split units 1407 and 1408 are independent from each other. Accordingly, there is no need to propagate signals in order in the signal propagation direction, therefore producing the advantage of requiring a less length of delay calculation processing time.
However, the first delay calculation method has some problems (FIG. 15). The problems of the first delay calculation method will be described below in detail.
Suppose here that the wire 1402 is several times greater than a wire 1410 in resistance and capacitance. In the already-described first delay calculation method, calculations are performed wherein the split units 1407 and 1408 are independent from each other, so that the output signal waveform 1404 of the instance 1400 which drives the wire 1402 of greater resistance and capacitance becomes dull, while on the other hand the output signal waveform 1406 of the instance 1401 which drives the wire 1410 of smaller resistance and capacitance is calculated as a signal waveform which sharply transits.
However, actually a signal waveform propagates in the signal waveform propagation direction. As a result, the actual output signal waveform of the instance 1401 differs from the output signal waveform 1406 as shown in FIG. 15(b). The output signal waveform of the instance 1401 is influenced by the dull output signal waveform 1404 of the instance 1400 and becomes a signal waveform 1500 which is much duller than the aforesaid sharp signal waveform.
As to this point, the results derived from actually-performed circuit simulations are shown in FIG. 17, wherein the wire 1402 has a capacitance of 250 f and a resistance of 500 xcexa9 while the wire 1410 has a capacitance of 5 f and a resistance of 10 xcexa9 and the logic of each instance 1400 and 1401 is an inverter. In FIG. 17, the reference numeral 1700 is a waveform diagram showing a circuit simulation result when signal waveform propagation is taken into consideration and the reference numeral 1701 is another waveform diagram showing a circuit simulation result when signal waveform propagation is not taken into consideration. The reference numeral 1702 is the input signal waveform of the instance 1401. Referring to the waveform diagram 1700 (i.e., the upper waveform diagram in FIG. 17) in which the RC of the wire 1402 connected to the input terminal of the instance 1401 is great, the input signal waveform 1702 of the instance 1401 becomes dull. Such a dull signal waveform propagates through the instance 1401 and is calculated as an output signal waveform 1703. Referring to the waveform diagram 1701 (i.e., the lower waveform diagram in FIG. 17) in which the RC of the wire 1402 connected to the input terminal of the instance 1401 is small, the input signal waveform 1702 of the instance 1401 is sharp. Such a sharp signal waveform propagates through the instance 1401 and is calculated as an output signal waveform 1704. The two output signal waveforms 1703 and 1704 are compared and the result shows that the output signal waveform 1704 is shaper than the output signal waveform 1703. A difference in slew between the two output signal waveforms is calculated and the difference is equivalent to as much as about 40% when a 20% and a 80% value of the supply voltage in each waveform are linearly approximated to serve as a slew. From this, in this conventional delay calculation tool, when a wire that is connected to an output terminal of cell2 is determined, decision is made uniquely, regardless of the input signal waveform. This results in poor delay calculation accuracy.
As described above, the first delay calculation method is not a delay calculation method which performs calculations along the signal propagation direction, in other words the split unit 1407 is first calculated and then the calculation result is used to calculate the split unit 1408. This therefore provides several merits such as eliminating the need for performing path retrieval toward the signal propagation direction, achieving reductions in processing time to reduce the delay calculation processing time. However, there are some demerits. One of the demerits is that the accuracy of delay calculations is poor for circuits with wires whose resistance and capacitance undergo considerable variation, as shown in FIG. 15(a).
Next, the second delay calculation method will be described by making reference to FIG. 16.
The delay calculation method or FIG. 16(a) is characterized in that both the signal waveform propagation between the input and output of the wire 1402 and the signal waveform propagation between the input and output of each of the instances 1400 and 1401 are calculated.
More concretely, in the instance output signal waveform calculation step, suppose that the instance 1400 drives the wire 1402 and the instance 1401, and then a circuit equation at the output terminal of the instance 1400 is set up to calculate an output signal waveform 1600 of the instance 1400 (FIG. 16(b)).
The second delay calculation method of FIG. 16 is different from the first delay calculation method of FIG. in that the influence of the input signal waveform 1403 of the instance 1400 is incorporated into the circuit equation.
The input signal waveform 1403 is a signal waveform calculated from the drive power of an instance that drives the instance 1400 and the input signal waveform of that instance, the input terminal capacitance of the instance 1400, and the resistance and capacitance components of a wire that is connected to the input terminal.
This is followed by a wire output signal waveform calculation step. In the wire output signal waveform calculation step, the circuit equation at the output terminal of the wire 1402 at the time when the output signal waveform 1600 propagates through the wire 1402 is solved to calculate an input signal waveform 1601 of the instance 1401.
These two steps are repeatedly performed on every instance and wire, thereby making it possible to calculate signal waveforms at the input and output terminals of all the instances. From these calculated signal waveforms, both the instance delay time and the wire delay time can be calculated.
In FIG. 16, the reference numeral 1602 is an output signal waveform of the instance 1401.
One merit of the second delay calculation method is that, as shown FIG. 16(c), when dividing a wire and an instance that is connected to the wire as single split units 1407 and 1408, respectively, there is held dependency between the split units 1407 and 1408.
In other words, prior to calculating the split unit 1408, the split unit 1407, which is earlier in the signal propagation sequence, is calculated and then the result is used to calculate the split unit 1408.
Delay calculations are carried out according to the signal propagation sequence. This produces demerits. Since, in addition to the delay calculation processing, it is required to determine a signal propagation sequence and to propagate information necessary for delay calculations according to the determined signal propagation sequence, this will take extra delay calculation processing time. On the other hand, there is a merit of providing considerably excellent delay calculation accuracy.
As described above, as a concrete delay calculation method for use in the delay calculation step S1302, there are several delay calculation techniques. Generally, both of the above-described delay calculation methods are not used and only one of them is usually used.
However, there is a procedure in which the delay calculation method of FIG. 14 is used for delay calculation of an entire LSI circuit and, with respect to clocks and critical paths which require very severe timing, information necessary for delay calculation about their corresponding portions is extracted and the delay calculation of FIG. 16 is used to perform delay calculations again.
As already described hereinbefore, it is not guaranteed that the layout step generates a layout shape allowing a delay calculation algorithm used in the subsequent delay calculation step to perform high-accuracy delay calculation. This produces the problem that there may be generated a to layout form causing delay calculation difficulties to the delay calculation algorithm. As a result, the delay calculation accuracy for such a layout becomes poor, which causes the design procedure to return back to a particular design step.
Further, the delay calculation method of FIG. 14 suffers the problem that the accuracy of delay calculation for a circuit having a configuration with wires whose resistance and capacitance undergo considerable variation becomes poor. On the other hand, the delay calculation method of FIG. 16 also suffers the problem that it is required to perform path retrieval in the signal propagation direction. This results in an increased length of delay calculation processing time. However, most of the presently-used design flows employ only one of the delay calculation methods of FIGS. 14 and 16 and fail to make good utilization of both of them in effective manner. In addition, in the conventional techniques there exists no index for effectively and properly using these two delay calculation methods during the layout stage.
Accordingly, an object of the present invention is to provide an index for distinguishing between the use of a delay calculation method which deals in detail with signal propagation between the cell input and output terminals and the use of a delay calculation method which does not deal with signal propagation between the cell input and output terminals.
In a semiconductor integrated circuit formed of a plurality of cells connected by wires, the present invention provides a cell delay time calculation method for cell delay time calculation. The cell delay time calculation method of the present invention comprises a circuit simulation step of (a) inputting a transistor level net list of each cell, (b) varying at least one of the slew of an input signal waveform of each cell and the magnitude of a load capacitance which is connected to an output terminal of each cell, (c) performing a circuit simulation of each cell, and (d) obtaining an output signal waveform of each cell under a respective simulation condition, and a dependence calculation step of calculating, based on each simulation condition and each cell output signal waveform obtained in the circuit simulation step, the dependence of the slew of each cell output signal waveform upon at least one of the input slew rate and the load capacitance, wherein based on the dependence calculated in the dependence calculation step a delay time of each cell is calculated by distinguishing between the use of a delay calculation expression with consideration taken to the propagation of signal waveforms between each cell""s input and output terminals and the use of another delay calculation expression without consideration taken to the propagation of signal waveforms between each cell""s input and output terminals.
In the dependence calculation step of the cell delay time calculation method, (i) the relationship between the cell input slew rate/load capacitance and the cell output signal waveform slew is represented in the form of a correlation table for each cell, (ii) from the correlation table, a region, whose degree of the dependence of the output signal waveform slew upon the input slew rate/load capacitance is higher than a given dependence threshold level, is classified as a high-dependence region, while a region, whose degree of the dependence of the output signal waveform slew upon the input slew rate/load capacitance is lower than the given dependence threshold level, is classified as a low-dependence region, and (iii) the classified correlation table is held as a dependence table.
In the cell delay time calculation method, the dependence table is stored in a delay library of each cell. In the cell delay time calculation method, the dependence calculation step includes an output signal waveform extraction step of (a) inputting a simulation result of the circuit simulation step and (b) extracting an output signal waveform group of each cell, an output signal waveform slew calculation step of (a) inputting the output signal waveform group, (b) subjecting all signal waveforms in the output signal waveform group to linear approximation for slew calculation, and (c) generating an output signal waveform slew group, a table generation step of generating, for each cell, a table indexed by input slew rate and load capacitance connected to output terminal, a correlation table generation step of embedding each of the output signal waveform slews of the output signal waveform slew group in the table for formation of the correlation table, and a classification step of (a) comparing each of the output signal waveform slews in the correlation table against a slew having a given value corresponding to the dependence threshold level and (b) classifying the correlation table into a high-dependence region and a low-dependence region.
The cell delay time calculation method further comprises a first delay calculation step of (a) inputting a gate level net list of parasitic capacitances and resistances extracted from a layout result of a semiconductor integrated circuit containing a plurality of cells and a delay library storing delay times of the plurality of cells and (b) calculating the delay time of the plurality of cells and the wires, the slew of the input signal waveform of each cell, and the load capacitance of each cell that is connected to each cell""s output terminal, for obtaining input/output terminal information and a dependence decision step of (a) inputting the net list, the delay library, and the I/O terminal information, (b) calculating, for each cell, the dependence of the output signal waveform slew upon the input slew rate and the load capacitance, and (c) deciding, for each cell, in which of the high- and low-dependence regions of the dependence table the calculated dependence belongs, wherein as to a cell whose dependence belongs in the low-dependence region a first delay calculation expression without consideration taken to the propagation of signal waveforms between the cell""s input and output terminals is used for delay time calculation, while as to a cell whose dependence belongs in the high-dependence region a second delay calculation expression with consideration taken to the propagation of signal waveforms between the cell""s input and output terminals is used for delay time calculation.
The cell delay time calculation method further comprises a net list split step of (a) generating a first net list of information about a cell whose dependence belongs in the low-dependence region, resistance and capacitance information about wires connected to the cell""s input and output terminals, and connection information about all cells connected to the wires and (b) generating a second net list of information about a cell whose dependence belongs in the high-dependence region, resistance and capacitance information about wires connected to the cell""s input and output terminals, and connection information about all cells connected to the wires, a second delay calculation step of (a) calculating a first delay calculation result with the first delay calculation expression for the first net list and (b) calculating a second delay calculation result with the second delay calculation expression for the second net list, and a delay information synthesis step of combining the first delay calculation result and the second delay calculation result to generate a single delay calculation result.
In the cell delay time calculation method, the dependence decision step includes a high-dependence instance extraction step of (a) inputting the delay library, the I/O terminal information, and the net list, (b) extracting, for each cell contained in the net list, an input slew rate and a load capacitance from the I/O terminal information, (c) collating the dependence of the slew of an output signal waveform corresponding to the input slew rate and the load capacitance with the dependence table, and (d) registering a cell whose dependence belongs in the high-dependence region as high-dependence instance information, and a first waveform propagation flag set step of (a) inputting the high-dependence instance information and (b) setting, with respect to a cell contained in both the net list and the high-dependence instance information, a first waveform propagation flag as information that should belong in the first net list.
In the cell delay time calculation method, the net list split step includes a waveform propagation flag addition net list generation step of adding the first waveform propagation flag to the net list to generate a first flagged net list, a second waveform propagation flag set step of (a) setting a second waveform propagation flag to a cell that is connected to a cell to which the first waveform propagation flag has been set and (b) adding the second waveform propagation flag to the first waveform propagation flag addition net list to generate a second waveform propagation flagged net list, and a split step of (a) inputting the second waveform propagation flagged net list, (b) extracting a cell to which the first or second waveform propagation flag is not set and a wire that is connected to the cell to generate a first net list, and (c) extracting a cell to which the first or second waveform propagation flag is set and a wire that is connected to the cell to generate a second net list.
In the cell delay time calculation method, the second waveform propagation flag set step includes inputting a propagation stage count threshold level of a predetermined number of stages, selecting cells up to the predetermined number of stages of the propagation stage count threshold level as a cell that is connected to a cell to which the first waveform propagation flag has been set, and setting the second waveform propagation flag to the selected cells.
Further, the present invention provides a semiconductor integrated circuit layout optimization method for optimally laying out a semiconductor integrated circuit formed of a plurality of cells connected by wires. The semiconductor integrated circuit layout optimization method of the present invention comprises a layout step of (a) inputting a net list and a delay library of the plurality of cells, (b) generating placement/wiring routing information of the plurality of cells, and (c) generating RC information of parasitic elements of the placement/wiring routing information, an input/output terminal information extraction step of (a) inputting the RC information and the delay library and (b) calculating, for each cell, an input slew rate and a load capacitance that is connected to an output terminal of each cell, for extracting input/output terminal information, an instance extraction step of (a) inputting the I/O terminal information and the delay library, (b) calculating, for each cell, the dependence of the slew of an output signal waveform upon the input slew rate and the load capacitance, and (c) registering a cell whose dependence is higher than a predetermined dependence threshold level as instance information, and a constraint step of subjecting the cell registered as the instance information to re-layout so that the dependence of the cell becomes lower than the dependence threshold level.
In the semiconductor integrated circuit layout optimization method, the constraint step includes generating a layout constraint for use in re-layout of the cell registered in the instance information, and returning back to the layout step to perform the cell re-layout so as to meet the generated layout constraint.
In the cell delay time calculation method of the present invention, the dependence of an output signal waveform of a cell upon the input slew rate and cell load capacitance of the cell, i.e., a parameter showing signal waveform propagation dependence between the cell input and output terminals, is calculated. Then, based on the dependence thus calculated, it is determined which one of the delay calculation methods (i.e., the method that deals with signal waveform propagation between the cell input and output terminals and the method that does not deal with signal waveform propagation between the cell input and output terminals) is suitable for delay calculation. Then, according to the cell input slew rate and the load capacitance connected to the cell output terminal, a delay calculation tool with a high-accuracy delay calculation algorithm mounted therein is used for a portion that requires severe consideration for signal waveform propagation so as to calculate delay time at high accuracy. On the other hand, for a portion that does not require severe consideration for signal waveform propagation, a high-speed delay calculation tool, which is inferior in accuracy to the foregoing delay calculation tool, is used. Accordingly, the present invention is able to provide a high-speed and high-accuracy delay calculation method for delay calculation of an entire LSI circuit.
Further, in the semiconductor integrated circuit layout optimization method of the present invention, the dependency of the output signal waveform of a cell upon the input slew rate and load capacitance of the cell is calculated. If the dependence of a cell exceeds a predetermined dependence level, then the cell is subjected to re-layout so that the cell dependence becomes lower than the predetermined dependence level. This makes it possible to calculate delay times at high accuracy by using only a delay calculation tool having an algorithm that does not deal with signal waveform propagation between the cell input and output terminals.